Computer Systems practice questions

Answer: A) Conflict misses

Raising associativity at a fixed capacity mainly reduces conflict misses, because blocks that map to the same set can coexist. It does not reduce compulsory or capacity misses, and it tends to increase hit time slightly.

• ACorrect. With more ways per set, blocks that map to the same set can stay in the cache together instead of evicting one another. This reduces conflict misses.
• BIncorrect. Compulsory (cold) misses happen on the first access to a block, whatever the cache organization. Larger blocks or prefetching address them, not associativity.
• CIncorrect. Capacity misses are the ones that would happen even in a fully associative cache of the same size, because the working set does not fit. With capacity fixed, adding associativity does not reduce them.
• DIncorrect. Higher associativity usually increases hit time slightly, because more tags must be compared and a way must be selected through a multiplexer.

Answer: B) Tracks the top of the call stack in memory

• AIncorrect. That's the program counter.
• BCorrect. It changes on push, pop, calls and returns.
• CIncorrect. That's a data register.
• DIncorrect. That isn't its role.

Answer: B) 0.5 ns

• AIncorrect. That's for 500 MHz.
• BCorrect. 1/(2 × 10⁹ Hz).
• CIncorrect. Recheck the reciprocal.
• DIncorrect. Recheck the reciprocal.

Answer: A) Each typically corresponds one-to-one with a machine instruction, produced by an assembler

Assembly language is a symbolic form of machine code. An assembler generally translates each instruction into exactly one machine instruction, with exceptions such as macros and pseudo-instructions.

• ACorrect. An assembly mnemonic and its operands usually encode exactly one machine instruction. Macros and some pseudo-instructions can expand into several instructions, but these are exceptions to the general one-to-one rule.
• BIncorrect. One-to-many translation is typical of high-level language statements processed by a compiler, not of ordinary assembly instructions.
• CIncorrect. Bytecode and virtual-machine interpretation belong to languages such as Java. Assembly is specific to one processor and is assembled into native machine code.
• DIncorrect. Microcode is internal to the processor's implementation and is not written by the programmer. Assembly targets the instruction set architecture, meaning the machine instructions.

Answer: D) 1.33

• AIncorrect. That would be a slowdown.
• BIncorrect. The serial part limits speedup.
• CIncorrect. That isn't the calculation.
• DCorrect. 1/(0.5 + 0.5/2).

Answer: A) Volatile

• ACorrect. It loses data without power.
• BIncorrect. DRAM is volatile.
• CIncorrect. It's read-write.
• DIncorrect. It's much faster.

Answer: C) Only when it's evicted

• AIncorrect. It's written when evicted.
• BIncorrect. That's write-through.
• CCorrect. Write-through writes on every store.
• DIncorrect. It's written at eviction.

Answer: D) k

• AIncorrect. That would slow it down.
• BIncorrect. Pipelining overlaps instructions.
• CIncorrect. That isn't realistic.
• DCorrect. Each stage works on a different instruction.

Answer: B) 6 ns

• AIncorrect. Add the hit time.
• BCorrect. 1 + 0.05(100).
• CIncorrect. Weight the miss penalty by the miss rate.
• DIncorrect. Multiply the penalty by the miss rate.

Answer: A) Keeping active pages in RAM and the rest on disk, loading them on page faults

Virtual memory uses paging to keep only the active pages in physical RAM and the rest on disk, swapping pages in on demand. Caches, TLBs and interleaving improve speed but do not add addressable capacity.

• ACorrect. Virtual memory maps virtual pages to physical frames. Pages that are not resident sit on secondary storage and are brought into RAM when a page fault occurs, so the disk works as an extension of main memory.
• BIncorrect. Caches hold copies of data that is already in main memory to cut access time. They do not let a program address more memory than physical RAM.
• CIncorrect. The TLB is a small cache of recent virtual-to-physical address translations. It speeds up address translation but stores no program data.
• DIncorrect. Interleaving improves memory bandwidth by overlapping accesses to different banks. Total capacity stays at the installed physical RAM.